Programmable integrated circuits (ICs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of programmable IC, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of programmable IC is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable ICs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other programmable ICs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These programmable ICs are known as mask programmable devices. Programmable ICs can also be implemented in other ways, e.g., using fuse or antifuse technology. The phrase “programmable IC” can include, but is not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of programmable IC includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Circuit designs are implemented within a programmable IC by mapping constructs of the programmatic circuit description to hardware elements available on the programmable IC. The mapped constructs then can be placed. That is, the mapped constructs can be assigned to particular hardware elements, each having a defined location, on the programmable IC. The various elements can be connected using the programmable interconnect fabric during the routing process.
Achieving timing closure of the circuit design with respect to map, place, and route refers to achieving timing for internal signal paths of the circuit design. Timing closure for external paths, e.g., the I/O interface of the programmable IC, still must be achieved. The timing of the I/O interface, which includes data signals entering the programmable IC and data signals leaving the programmable IC, as well as clock signals, often must be altered to ensure that the circuit design, once implemented within the programmable IC, functions properly. Presently, tuning the I/O interface is a manual, time consuming process. Any modification to the underlying circuit design usually necessitates retuning of the I/O interface. Whenever any circuit design is to be implemented for a variety of different programmable IC architectures, the I/O interface tuning process must be started anew for each different programmable IC architecture since the tuning parameters realized for one programmable IC architecture usually do not work when the circuit design is migrated to another different programmable IC architecture.
One difficulty in tuning I/O interfaces is that within some programmable ICs, the clock is distributed throughout the device using dedicated, global clock routing resources. These resources are independent of the routing resources available for implementing the user-specified portion of the circuit design. It is often the case that the clock signals will incur a different latency, often larger, than the input delays observed on data signals entering the programmable IC. In some cases, the difference may be on the order of 4 to 5 nanoseconds. The clock and/or the data must be delayed to achieve the necessary I/O interface timing closure.
Taking an example, some cores, such as a core implementing Ethernet Reduced Gigabit Media Independent Interface (RGMII), must operate with the clock falling in the center of a window only 2 nanoseconds in width. Tuning the I/O interface to meet such a tolerance typically requires significant manual adjusting of the I/O interface parameters and multiple iterations of the design flow. Once timing closure is achieved for a core for one programmable IC architecture, however, the I/O interface tuning process must be started anew for every other programmable IC architecture for which the core is to be developed.
In general, a core refers to a pre-designed, programmatic description of hardware that performs a particular function. A core can include a predetermined set of configuration bits that program the programmable IC to perform one or more functions. Alternatively, a core can include source code or schematics that describe the logic and connectivity of a design. Typical cores can provide, but are not limited to, digital signal processing (DSP) functions, memories, storage elements, and math functions. Some cores include an optimally floorplanned layout targeted to a specific family of programmable ICs. Cores can also be parameterizable in that the user may enter parameters to activate or change certain functionality of the core.